library ieee;
use ieee.std_logic_1164.all;
use work.components_pack.all;
use work.fir_pack.all;

entity tap is
	generic(nr : integer);
	port(
		clk, rst : in  STD_LOGIC;
		x_in     : in  STD_LOGIC_VECTOR(22 downto 0);
		add_in   : in  STD_LOGIC_VECTOR(29 downto 0);
		dff_out  : out STD_LOGIC_VECTOR(22 downto 0);
		add_out  : out STD_LOGIC_VECTOR(29 downto 0)
	);
end entity tap;

architecture RTL of tap is
	signal dffOut  : STD_LOGIC_VECTOR(22 downto 0);
	signal multOut : STD_LOGIC_VECTOR(29 downto 0);
	type array_int is array (15 downto 0) of integer;
	constant multiplicands : array_int := (-1, 0, 1, -3, -9, -2, 30, 63, 63, 30, -2, -9, -3, 1, 0, -1);
begin
	adder_inst : component adder
		generic map(w1 => 30,
			        w2 => 30)
		port map(in1    => add_in,
			     in2    => multOut,
			     output => add_out);
	fixed_mult_comb_inst : component fixed_mult_comb
		generic map(w            => x_in'length,
			        w_m          => COEFF_WIDTH,
			        multiplicand => multiplicands(nr + 1))
		port map(input  => dffOut,
			     output => multOut);

	dff_inst : component dff
		generic map(w => x_in'length)
		port map(clk => clk,
			     rst => rst,
			     d   => x_in,
			     q   => dffOut);

	dff_out <= dffOut;
end architecture RTL;
